Connected with the strongest chip industry chain science popularization, the depth analysis of chip self-controllable (1)
Etching is the process of removing unnecessary materials from the wafer surface. Etching is performed after photolithography. Mask aligner light is used to copy the circuit structure on the mask onto the silicon wafer, and the etching machine micro-carves the circuit structure copied onto the silicon wafer, carving grooves and contact points so that the circuit can be put in. According to the etching process, it can be divided into dry etching and wet etching. The dry etching mainly uses reactive gas and plasma for etching, while the wet etching process mainly involves soaking etching materials in etching solution for etching. Dry etching is the mainstream in semiconductor etching, accounting for 95% of the market. Its biggest advantage is that it can realize anisotropic etching, that is, it can control only the materials in the vertical direction to be etched without affecting the materials in the horizontal direction, thus ensuring the fidelity of fine graphics. Due to uncontrollable etching direction, wet etching can easily reduce the line width and even destroy the circuit itself in advanced processes, resulting in poor chip quality. At present, the principle of multi-template process is widely adopted, that is, the required feature size is achieved by multiple deposition and etching processes. For example, the etching steps required for 14nm process reach 64 times, which is 60% higher than that for 28nm. The etching steps required for 7nm process are as high as 140 times, which is 118% higher than that for 14nm. The following figure shows the principle of multiple etching.
Like mask aligner, there are relatively few etching machine manufacturers, and the representative enterprises are Lam Research (Pan Lin Semiconductor), AMAT (Applied Materials) and TEL (Tokyo Electronics) in the United States. These three companies account for 94% of the global market share of semiconductor etchers, while other participants only account for 6%. Among them, Lam Research accounts for as much as 55%, which is the industry leader, and Tokyo Electronics and Applied Materials account for 20% and 19% respectively. At present, the representative companies of etching equipment are Zhongwei Company, North Huachuang Company, etc. China Micro Company is a leader, and the process node has reached 5nm. Among the top ten wafer companies in the world, China Micro Company has entered six of them, and as a partner of TSMC, it has cooperated to verify advanced technologies such as 14nm/7nm/5nm.
Based on this, if we are unable to make changes in the field of mask aligner at present, then the etching machine that already has certain advantages is bound to become the pioneer of domestic substitution.
2.2 Process
The manufacturing process of the chip requires more than 2,000 technological processes. Below, we briefly introduce the chip manufacturing process according to the eight steps.
1.Lithography (optical development)
Lithography is the process of exposure and development, which converts the pattern on the mask to the wafer under the photoresist. Lithography mainly includes photoresist coating, baking, mask alignment, exposure and development. Exposure methods include: ultraviolet, extreme ultraviolet, X-ray, electron beam, etc.
2.Etching (etching)
Etching is a technique of removing materials by chemical reaction or physical impact. Dry etching uses the physical action produced by plasma striking the wafer surface, or the chemical reaction between plasma and atoms on the wafer surface, or the combination of both. Wet etching uses chemical solution, and achieves the purpose of etching through chemical reaction.
3. Chemical vapor deposition (CVD)
Chemical reactions such as CVD heat energy, discharge or ultraviolet light irradiation are used to deposit reactants on the wafer surface to form a stable solid film. CVD technology is widely used in chip manufacturing, such as dielectrics materials, conductors or semiconductors, etc., which can be completed by CVD technology.
4. Physical vapor deposition (PVD)
PVD is a physical process rather than a chemical process. Generally, argon and other gases are used. After argon ions are accelerated in vacuum to hit the sputtering target, the target atoms can be sputtered out one by one, and the sputtered materials can be deposited on the wafer surface like snowflakes.
5. Ion Implant (ion implant)
Ion implantation can implant dopants into specific areas of semiconductor components in ion form to obtain accurate electrical characteristics. The ions are accelerated to sufficient energy and speed to penetrate (implant) the thin film and reach a predetermined implantation depth. Ion implantation can precisely control the dopant concentration in the implanted region.
6. Chemical mechanical polishing (CMP)
Chemical polishing technology has two functions: mechanical polishing of abrasive substances and chemical polishing of acid-base solutions, which can make the wafer surface completely planarized, so as to facilitate the subsequent film deposition.
7. wash
The purpose of cleaning is to remove metal impurities, organic pollution, dust and natural oxides; Reduce the surface roughness; Almost all processes need to be cleaned before and after.
8. Die Saw
Wafer cutting is to cut and separate the die on the processed wafer, which is convenient for the subsequent packaging test.
Although the processes of different Foundry factories are roughly the same, the different process control capabilities make the difference in advanced processes of various manufacturers. As the process goes into 5nm, there are only a handful of chip manufacturers that can mass-produce 5nm chips. At present, only*and SAMSUNG can mass-produce 5nm chips. The infinite wisdom and abundant financial resources of Foundry are hidden in more than 2,000 technological processes, which does not mean that with advanced equipment, qualified chips can be made. Although advanced manufacturing process is the direction of technological development, we can't ignore mature manufacturing process. Mature processes still have a large market share. The figure below shows the Top list of global foundry manufacturers in terms of mature process (node ≥40nm) capacity.
It can be seen that the top four manufacturers in mature process capacity are*(market share 28%), UMC (13%), SMIC (11%) and Samsung (10%). The mature process will be very popular in 2020, and the production capacity will be seriously short, which will bring huge business opportunities to major wafer foundries. Judging from the industrial development situation in 2021, this shortage will not be alleviated in the near future.
2.3 material
There are thousands of materials used to produce integrated circuits, so we will analyze the most typical silicon wafer and photoresist.
Silicon wafer is the grain of IC industry, and it is the most important and basic IC material. More than 90% of chips are made on silicon wafer. At present, 300mm silicon wafer is the mainstream material for chip manufacturing, and its usage ratio exceeds 70%. At one time, China's 300mm semiconductor silicon wafers were 100% imported, which was the main bottleneck of China's IC industry chain construction and development. The world's major suppliers of semiconductor silicon wafers include Shin-Estu, SUMCO, Siltronic, SK Siltron,*Province, China, Universal Wafer and Hejing Technology, etc. The global market share of the five major wafer suppliers reached 92%, among which Shinetsu Chemical of Japan accounted for 27%, Shenggao of Japan accounted for 26%, Universal Wafer of*Province accounted for 17%, Silitronic of Germany accounted for 13% and SK Siltron of South Korea accounted for 9%. The following table lists the top 10 silicon wafer suppliers in the world for reference.
Domestic situation, the average annual compound growth rate of semiconductor silicon wafer sales in Chinese mainland reached 41.17%, far higher than the global semiconductor silicon wafer market of 25.75% in the same period. However, this market is not in the hands of local manufacturers, and there is still a lot of room for domestic wafer manufacturers to develop in today's domestic industrial chain.
Photoresist is the most important consumable in lithography process, and the quality of photoresist has an important influence on lithography process. Photoresist can be divided into semiconductor photoresist, panel photoresist and PCB photoresist. Among them, semiconductor photoresist has the highest technical barrier. At present, the main photoresist companies in the world are Japan Synthetic Rubber (JSR), TOKyo Yinghua (Tok), ShinEtsu Chemical (Shinetsu), FUJI Electronics (Fuji), Rohm&Hass of the United States, etc., and their market concentration is very high, accounting for more than 85% of the market. The following figure shows the market share of photoresist enterprises. High-resolution semiconductor photoresist is the material with the highest technical barrier among semiconductor chemicals, and the technology of Japanese and American enterprises is twenty to thirty years ahead of that of domestic enterprises. From the perspective of photoresist technology level, domestic enterprises have explored a road of independent research and development under the conditions of lack of experience, professional and technical talents and key upstream raw materials and equipment. It is still difficult to break through the high-end photoresist technology in a short time, and there is still a long way to go. In the field of PCB, domestic photoresist has a certain mass production capacity and has been supplied to mainstream manufacturers.
03
Packaging test
Packaging is the last link in the three major industries of integrated circuits. Generally speaking, the technical content and implementation difficulty of packaging test are lower than those of the former two, but with the emergence and rapid development of SiP and advanced packaging technology, it is necessary to redefine the packaging and testing of chips. On the basis of the original three features of SiP package: chip protection, scale amplification and electrical connection, SIP package adds three new features: increasing the functional density, shortening the interconnection length and reconfiguring the system, so its complexity and implementation difficulty are greatly improved compared with the traditional package. At the same time, SiP and advanced packaging bring new opportunities and challenges to package testing.
3.1 chip packaging
We analyze chip packaging from two aspects: packaging design and product packaging.
1）Packaging design
There is no concept of Integration in the previous packaging, and the packaging design is relatively simple, with low requirements for tools. Auto CAD is a commonly used packaging design tool. With the emergence of MCM and SiP technologies, the packaging design has become more and more complex. In addition, the market acceptance of SiP, advanced packaging, Chiplet and heterogeneous integration concepts is getting higher and higher, and the complexity and flexibility of the integration within the package have risen sharply, and the requirements for the packaging design have become higher and higher. At present, there are only Cadence and Siemens EDA(Mentor) for SiP and advanced packaging design tools. Cadence is an established EDA provider of packaging design, which has a high market share and high loyalty of users. Siemens EDA(Mentor) is a rising star in the field of packaging design, but its technological advancement reflects the characteristics of "the late wave". Industry leaders TSMC, Intel, SAMSUNG have chosen Siemens EDA as their first choice tool for advanced packaging (HDAP), which mainly lies in two aspects: advanced design tools and powerful verification tools. First of all, let's talk about design tools. In a technical forum, I said, "Different from traditional packaging design, advanced packaging and SiP design have high requirements for 3D environment. The 3D design environment lies not in whether it looks intuitive and gorgeous, but in the accurate description of objective elements, including bonding wires, cavities, chip stacks, silicon adapter boards, 2.5D integration, 3D integration, Bump ..." At this point, Siemens EDA's SiP and advanced package design tools have left its competitors far behind. The following figure is a 3D screenshot of the package design in XPD, an advanced package layout design tool. In four groups of chip stacks, each group of five chips (4HBM+1Logic) are connected together by 3D TSV, and integrated with GPU on a silicon adapter board (2.5D TSV), which is integrated with resistors, capacitors, etc. on the package substrate.
Screenshot of advanced package design in XPD (3D) This design includes 3D integration, 2.5D integration, flip-chip, Bump, multi-substrate integration, etc., which has been accurately realized in XPD design environment. Advanced package verification tools include electrical verification and physical verification. Electrical verification contains more than 80 rules, which check and verify the whole system in terms of signal integrity, power integrity, EMIEMC and other electrical aspects. Physical verification is based on IC verification tool Calibre, which integrates Calibre 3D STACK and is specially used for physical verification of 3D advanced packages. With the increasing integration and design complexity in the package, the requirements for tools are higher and higher. In addition, in the field of advanced packaging, the synergy between package design and chip design is increasing, and there is a trend of gradual integration to some extent, so the requirements for collaborative design are also increasing. For detailed design methods and practical cases of SiP, microsystem and advanced packaging, please refer to the new book "Microsystem Based on SiP Technology" to be published by Electronic Industry Press. 2) According to different materials and processes, product packaging can be divided into three types: plastic packaging, ceramic packaging and metal packaging. Plastic packaging is mainly based on organic substrates, and is mostly used in commercial products. It is small in size, light in weight and cheap, and has the advantages of mass production and low cost, but it is relatively poor in heat dissipation, stability and air tightness of chips. Ceramic packaging and metal packaging are mainly based on ceramic substrates. HTCC substrates are generally used for ceramic packaging, while LTCC substrates are mostly used for metal packaging. For high power consumption products, aluminum nitride substrates can be used. Ceramic packaging features include: good sealing performance, good heat dissipation performance, good resistance to extreme temperature, easy disassembly and easy problem analysis; Compared with metal packaging, it is relatively small in size, suitable for large-scale complex chips, and suitable for severe environmental applications such as aerospace and the like that require air tightness; But the price is expensive, the production cycle is long, and the weight and volume are larger than those of similar plastic products. Metal packaging features include: good sealing, good heat dissipation, easy disassembly and high flexibility; However, due to its relatively large volume, small number of pins, unsuitable for complex chips, high price, long production cycle, complex process and the need to assemble metal shell and substrate, it is mostly used in MCM design and widely used in aerospace field. Both ceramic and metal packages have cavity structures, which are detachable, easy to find faults and "zero" problems, so they are welcomed by users in aerospace and other fields.
3.2 chip testing
There are many chip testing items. Here, we focus on the systematic testing of machine testing.
Test machine
Generally, ATE(Automatic Test Equipment) automatic test equipment is used to test the chip, to test the basic functions and corresponding electrical parameters of the chip. The machine can provide the power supply, waveforms with different periods and time sequences, driving levels, etc. required by the device under test (DUT). Test Vector is logic 1 and logic 0 data applied to device pins for testing every clock cycle, which is represented by waveforms with timing characteristics and level characteristics, and is related to waveform shape, pulse width, pulse edge or slope, and the positions of rising and falling edges. The test vector can be based on the simulation vector of EDA tool (including input signal and expected output), which is optimized and converted to form ATE format test vector. The EDA tool is used to build the device model, and a Testbench simulation verification platform is established to provide test incentives, simulate and verify the results. The input incentives and output responses are stored, and ATE vector files are generated according to ATE vector format.
System testing, also known as board-level system testing, refers to simulating the real working environment of the chip, performing various operations on the chip to confirm whether its function and performance are normal. In addition to the machine test and system test, a series of tests and assessments are needed for the chip, including: thermal shock, temperature cycle, mechanical shock, frequency sweep vibration, constant acceleration, bonding strength, chip shear strength, steady life, sealing, internal water vapor content, moisture resistance and other tests. Only when all the tests are successfully passed, can a chip be considered successful, and it can be applied to the next step as a qualified product.
Self-controllable summary
Finally, combined with the following table, we make a simple summary of autonomy and controllability.
As can be seen from the table, we have a high degree of self-control in IC design process, SiP design, product packaging and chip testing; There is a certain degree of independent controllability in etching machine and chip process, but the degree of independent controllability in EDA, IP, mask aligner, silicon wafer, photoresist and other links is very low, so high-end chips are easily "stuck" because EDA, IP, mask aligner, silicon wafer and photoresist used in high-end chips almost all depend on imports. IC design process and SiP design, which are relatively controllable, almost all rely on imported EDA tools. In product packaging and chip testing, more than 80% of packaging equipment and testing equipment are imported equipment. In the process, high-end chips can't be produced independently. Considering these, we can't help being blindly optimistic, because the more we dig into the source, the lower the proportion of self-control. When others don't get stuck in their necks, don't be cocky, as if everything is under control; When others get stuck in their necks, don't suddenly find that their necks are all over their bodies! After reading this article, if someone tells you in the future that the chip he made is 100% self-controllable, we can analyze it one by one from the above links. Which links are really self-controllable in the process of a chip from the initial conception to the final product? Which links are still stuck in the neck?
Only by truly recognizing one's own shortcomings, seeking truth from facts, being steadfast, one step at a time, and persevering, can we not fall behind in the fierce competition, thus reducing the occurrence of neck sticking!
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