If someone says to you, "Hey, the chip I made is 100% self-controllable!" Wait, don't be in a hurry to worship (believe) him first. Please read this article before you speak. ...
First of all, what is self-controllable? The most intuitive understanding is that when others "get stuck", they won't get stuck. The integrated circuit industry is usually divided into three fields: chip design, chip manufacturing and package testing. See the following figure:
We analyze them one by one. The chip design is mainly analyzed from three aspects: EDA, IP and design. Chip manufacturing is mainly analyzed from three aspects: equipment, technology and materials; Packaging is analyzed from packaging design, product packaging and chip testing.
01
Chip design
How to start a chip design?
First, you need tools (EDA), then you can start chip design with the help of existing resources (IP) and your own ideas and plans. Here, we will analyze the chip design from the chip design tools EDA, IP, and the design process of integrated circuits.
1.1 EDA
EDA(Electronic Design Automation) Electronic design automation, often refers to the software used for electronic design.
Someone once said to me, "What's wrong with EDA? Isn't it just a tool?" Yes, it is a tool, but without it, you can't design anything!
Today's large-scale integrated circuits can integrate more than 100 million transistors in a square millimeter the size of sesame seeds, and there are hundreds of millions of connecting networks among these transistors. Today's mainstream SoC chips have more than 10 billion transistors. If there is no accurate and powerful EDA tool, how can it be designed?
EDA is an essential tool for chip design. At present, Synopsys, Cadence and Mentor(Siemens EDA) occupy more than 90% market share. In the design of high-end chips below 10 nanometers, its share is even as high as 100%. That is to say, it is almost impossible to develop a chip below 10nm without the EDA tools of the above three companies.
The following table shows the current mainstream EDA tools in chip design:
Chip design is divided into design, simulation and verification, and the corresponding EDA tools are divided into design tools, simulation tools and verification tools. The design tool solves the problem of building the model, that is, from 0 to 1 (from scratch), while the simulation and verification tool solves the problem of confirming the model, that is, whether 1 is 1 or 0.9 or 1.1. Therefore, from the perspective of EDA development, it is more difficult to develop design tools. In addition, the larger the design scale, the higher the requirements of process nodes, and the more difficult it is to develop EDA tools. At present, domestic EDA tools have made some achievements in some simulation verification point tools, and they also have the full-process tools in analog circuit design. However, there is still a big gap between them and the three major manufacturers in the design of large-scale integrated circuits, especially in the design process of high-end digital chips.
1.2 IP
IP(Intelligent Property) stands for the meaning of intellectual property rights. In the industry, it refers to a pre-defined, verified, reusable module that can complete a specific function. IP is the basic unit of LSI, and SoC can even be said to be a multiplexing technology based on IP core. Generally, IP is divided into hard core, soft core and solid core. Generally, IP hard core has been mapped to a specific process, which has been verified by chip manufacturing. It has the characteristics of predictable area and performance, but it is less flexible. IP core is submitted in HDL, which is flexible, but unpredictable in performance. IP core optimizes its performance and area through layout or general process library, which is more flexible and predictable than hard core and soft core, and is a compromise between hard core and soft core.
The following table shows the top 10 IP providers in the world at present. It can be seen that China has two finalists in the top 10, but the combined market share of the two companies is only 3%, while ARM alone accounts for more than 40% of the market share, while American enterprises account for 30% of the market share. If ARM is acquired by Nvidia, the IP market will basically be the world of the United States. In addition, we also find that Synopsys and Cadence, the two largest EDA companies in the world, also occupy the second and third positions in the IP field.
The following figure shows the types of IP, in which processor accounts for 51%, interface IP accounts for 22.1%, digital class accounts for 8.1% and others account for 18.8%. ARM, the processor class, is the only one. Synopsys is the industry leader in interface IP.
1.3 design cycle
Chip design flow can be divided into digital IC design flow and analog IC design flow. Digital IC design process: chip definition → logic design → logic synthesis → physical design → physical verification → layout delivery. Chip Specification refers to making the function and performance index of the chip according to the requirements, and completing the design specification document. Logic Design refers to the realization of logic design at RTL(Register-Transfer Level) level based on hardware description language, and the correct function is verified by logic verification or formal verification. Logic Synthesis refers to the transformation of RTL into a gate-level netlist with a specific target, and the optimization of netlist delay, area and power consumption. Physical Design refers to the process of arranging and wiring the gate-level netlist according to constraints and finally generating the layout, which also includes: data import → layout planning → unit layout → clock tree synthesis → wiring.
Data import is the script file that guides the integrated netlist and timing constraints, and the library file provided by the foundry.
Layout refers to the process of planning the positions of input/output units, macro units and other major modules on the chip.
Cell layout is the process of automatically placing standard cells according to netlist and timing constraints.
Clock tree synthesis refers to the process of inserting clock buffer, generating clock network and minimizing clock delay and deviation. Wiring refers to the process of automatically connecting each unit according to the circuit relationship under the constraint conditions of the number of wiring layers, line width and line spacing.
Physical Verificaiton usually includes layout design rule check (DRC), layout schematic diagram consistency check (LVS) and electrical rule check (ERC). Tape Out refers to transferring layout files to the foundry to generate mask patterns and produce chips on the premise that all checks and verifications are correct. Analog IC design process: chip definition → circuit design → layout design → layout verification → layout delivery. Among them, chip definition and layout delivery are the same as digital circuits, while analog IC is different in circuit design, layout design, layout verification and digital circuits. Analog circuit design refers to the design of transistor-level analog circuit structure according to system requirements, and the function and performance of the circuit are verified by SPICE and other simulation tools. Analog layout design is to draw the layout geometry corresponding to the circuit diagram according to the design rules, and simulate the function and performance of the layout. Analog layout verification is to verify the process rules, electrical rules and the consistency check of layout circuit diagram. Here, let's make a simple summary:
Chip design: With the support of EDA tools, the whole process of chip design is completed by purchasing IP authorization+independent research and development (cooperative development) IP and following the strict simulation and verification process of integrated circuit design. In this process, EDA, IP and strict design process are indispensable.
At present, among these three elements, the design process is the first one that can realize self-control. The following table lists the top 10 chip design companies in the world for your reference.
02
Chip manufacturing
At present, chip manufacturing is the industry with the highest threshold in the integrated circuit industry. How do you look at the threshold? The higher the investment, the less players, the higher the threshold. At present, only TSMC, SAMSUNG and Intel are left in the manufacture of high-end chips. Below, we analyze the chip manufacturing from three aspects: equipment, technology and materials, and look for the gap between us and advanced manufacturing technology.
2.1 equipment
The manufacture of the chip needs more than 2,000 technological processes to complete, and each step depends on specific equipment to achieve it. There are three key processes in chip manufacturing: photolithography, etching and deposition. The three major processes are repeatedly circulated in the production process, and finally qualified chips are manufactured. Three key equipments are used in the three key processes, namely, mask aligner, etching machine and thin film deposition equipment. Three major equipments account for about 22%, 22% and 20% of all equipment investment, and they are the three semiconductor equipments with the highest proportion.
Take the most typical mask aligner and etching machine as examples to introduce and analyze the self-controllability.
photoetching machine
The principle of Mask aligner is actually like a slide projector, that is, the light is projected onto a wafer coated with photoresist through a mask (also called a mask) with a circuit diagram. In the late 1960s, Japanese Nikon and Canon began to enter this field, and mask aligner was not much more complicated than cameras at that time.
EVU mask aligner EUV extreme ultraviolet lithography (Extreme Ultra-Violet) is a new generation lithography technology using extreme ultraviolet (EUV) wavelength, with a wavelength of 13.5 nm. Because the lithography accuracy is several nanometers, EUV requires extremely high concentration of light, which is equivalent to holding a flashlight to illuminate the moon spot with no more than one coin. The reflection mirror is required to be 30cm long with fluctuation of less than 0.3nm, which is equivalent to the fluctuation of the railway track from Beijing to Shanghai of less than 1mm. An EUV mask aligner weighs 180 tons, has more than 100,000 parts, needs 40 containers for transportation, and takes more than one year to install and debug. In 2000, Japanese Nikon was the leader in mask aligner, and by 2009, ASML was far ahead with a market share of nearly 70%. At present, only ASML can provide the most advanced mask aligner. At home, Shanghai Microelectronics (SMEE) already has a mask aligner with a resolution of 90nm, and a new mask aligner is under development.
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