While theoretically feasible and partially validated by some fabs at the 7nm node, this approach requires several critical conditions to align simultaneously. Key among these is "overlay accuracy" in multi-patterning—precise alignment of patterns between multiple exposures.
Moreover, numerous other process techniques come into play, such as phase-shift masks, model-based optical proximity correction, etch techniques like self-aligned quadruple patterning, and even emerging directed self-assembly lithography technologies. These approaches offer possibilities for producing 5nm chips without relying solely on higher-resolution lithography.
Of course, adopting such methods entails high costs, so semiconductor fabs typically avoid using such extreme measures to mass-produce advanced-process chips. After all, mainstream solutions are typically selected based on market competition, ensuring that only the most commercially viable manufacturing methods endure.
Let's start with some foundational knowledge, but feel free to skip this part if you already have a systematic understanding of process nodes.
Is 5nm just a play on words?
To understand whether immersion lithography combined with multi-patterning can achieve 5nm, we first need clarity on what "5nm" refers to. Recently, there's been renewed debate on this topic, with claims that ASML has exposed the semiconductor fabs' strategies.
Before delving into the topic of line widths, it's crucial to understand the role of transistors and the significance of line width in this context.
Transistors use a gate to control the conduction and cutoff of circuits: conduction represents '1', while cutoff represents '0', enabling binary computation. The gate length (or channel length) directly impacts how quickly current can flow between the source and drain of the transistor. Smaller gate lengths enhance transistor performance, allowing for faster current flow and thus stronger chip performance.
Figure 1: Schematic diagram of the planar structure of a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor).
In the past, transistor gate length was defined as the line width, aligning with process node names, where lithography, deposition, etching, and diffusion were central processes for reducing line widths.
With the emergence of three-dimensional transistor structures like FinFETs and Nanosheets, the semiconductor industry has shifted focus to emphasizing equivalent performance. Despite being labeled as 14nm, these technologies have gate lengths far exceeding 14nm. For instance, Intel's 14nm process features a gate length of 24nm, while TSMC's 7nm process has a gate length of 22nm.
On the other hand, line width alone does not serve as a characteristic parameter for measuring transistor density. This is because even with small line widths, if the spacing between gates is large, the number of transistors that can be accommodated per unit area remains limited. To accurately depict component miniaturization, another crucial metric comes into play—pitch, as illustrated in the diagram below. For example, where previously 9 transistors fit within one unit area, reducing the pitch allows for accommodating 10 transistors.
Figure 2: Relationship between line width/gate length, pitch, and half-pitch.
In the 1990s, prior to 0.35μm, process nodes, half-pitch (the half of pitch), and gate lengths were all aligned. However, divergence between half-pitch, gate length, and nodes emerged thereafter. The relationship and evolution of nodes, half-pitch, and gate lengths can be clearly observed from the following chart.
Table 1: Correspondence of process nodes, half-pitch, and gate lengths across different years, units: nm
Returning to the initial topic, when we talk about 5nm, we're actually referring to its process node rather than its actual line width.
Many people like to say that the nanometer values claimed by various semiconductor giants today are merely marketing terms. Strictly speaking, this has been true for all process nodes twenty years ago. Ten years ago, when the industry entered the era of 14nm FinFET three-dimensional structures, it completely broke the association between nodes, pitch, gate length, and line width.
Without a unified standard, companies naturally use these terms to play with concepts. Samsung pioneered with its 14nm node, prompting*to quickly follow suit, though they conservatively labeled it as 16nm. Only Intel, self-proclaimed steadfast followers of Moore's Law, stubbornly adhered to traditional naming conventions for line widths until 2021 when they finally revised their node naming to align with competitors.
But is there a problem with this? In fact, there isn't any issue at all.
Transistors have long transitioned from planar to three-dimensional structures. If we translate the concept of line width into transistor density (MTr/mm2, meaning million transistors per square millimeter), we find that Moore's Law has not disappeared; it continues to operate in a different form—the density of transistors per unit area has consistently increased. Moore's Law originally stated that "the number of transistors per chip doubles every 18 months."
The Battle of Transistor Density in the Semiconductor Industry
The various characteristic dimensions of transistors are diverse and complex, with each manufacturer having different design definitions. Consequently, products from different manufacturers using the same process technology may not be entirely comparable.
Currently, the only intuitive way to compare differences in manufacturing processes is to return to the essence of Moore's Law and compare transistor density—that is, the number of transistors per unit area.
Table 2: Transistor Density per Square Millimeter at Various Nodes for Major Wafer Foundries, Partial Data Sourced from Third Parties
According to the data in the table, at the 14nm node, Intel, TSMC, and Samsung achieve approximately 0.3 billion transistors per square millimeter.
Starting from 10nm, Intel rebranded its 14nm+++ to Intel 10, keeping the name updated but reducing transistor density to the lowest among competitors. Samsung optimized their 10nm to an 8nm node, nearly matching TSMC's level.
In 2018, TSMC pioneered 7nm production using immersion lithography (1980Ci) and quad patterning. Samsung countered a year later with EUV lithography but faced yield issues due to unfamiliarity, leading them to abandon their Orion chips for Samsung phones, opting instead to use Qualcomm chips at a 30% lower cost than TSMC's, retaining Qualcomm as a major client. Meanwhile, Intel was still squeezing performance from 14nm+++, while TSMC dominated with 7nm.
TSMC's 7nm evolution from DUV-based N7, N7P to EUV-based N7+ and N6 achieved transistor densities rising from 0.91 to 1.16 billion. Samsung reached 0.95 billion, while Intel only achieved 1 billion transistor density in 2020.
In 2020, Samsung announced 5nm production with a minor increase in transistor density from 0.95 billion to 1.27 billion, and their enhanced 4nm version achieved 1.37 billion transistors, falling short of TSMC's initial 5nm at 1.5 billion and the improved N4P at 1.8 billion, which was a substantial upgrade from 7nm. Samsung faced similar challenges at the 3nm node.
In 2021, Intel renamed their nodes: 10nm became Intel 7, 7nm became Intel 4, and further nodes were refined to Intel 3, Intel 20A, and Intel 18A. CEO Pat Gelsinger's roadmap aimed to conquer three nodes over five years, although Intel 7 already leveraged their 10nm, and Intel 4 and Intel 3 represented refined versions of the same node.
Based on current understanding, Intel's progress with Intel 18A is likely delayed until at least 2026, while TSMC's first-gen 2nm could start production by late 2025. Apple's A19 chip in early 2025 will likely depend on TSMC's 2nm yield rates, following their early release of the first-gen 3nm A17 with marginal improvement. Notably, N4P and N3B densities at*were 1.8 billion and 1.9 billion, respectively, with modest gains.
Apple may change strategy this year, pushing*to explore deeper into 3nm potential. The A18, adopting N3P, marks an increase in density from 1.9 billion to 2.8 billion transistors compared to the A17, still 3nm, with competitor densities below 1.8 billion and low yield in small batches.
A noteworthy trend is the extension of Moore's Law from 18 to 24 months, slowing to 30 months post-7nm, with 7nm production in 2018, 5nm in 2020, 3nm in 2023, and anticipated 2nm in 2025, progressing approximately every two to three years. Technologically speaking, 1.4nm could maintain this pace, but beyond 1nm, node advancement may lengthen to over 40 months, impacting transistor count positively while scaling down linewidths.
Over the next 20 years, chip transistor totals will continue rapid growth, potentially surpassing original Moore's Law projections on single-chip power, exemplified by TSMC's forecast of a trillion transistors on a GPU within the next decade. Future advancements won't rely solely on process enhancements but also on optimized 3D structures, new 2D materials, and advanced packaging techniques, continuously boosting transistor counts effectively.
The mass production and yield rate have become a gray area.
Table 3: The major wafer fabs have a production timeline between 32/28nm and 14nm according to the technology roadmap, with an additional node at 22nm.
In the past, being the first to mass produce was a critical advantage in the fierce competition among Intel, Samsung, and TSMC. Whoever could achieve mass production first gained a significant edge.
However, today, there's a huge disparity in how each company defines their process nodes. For instance, while all claim to be at 5nm, the transistor densities can vary drastically. From this perspective, Intel poses a slight threat to TSMC, while Samsung has largely fallen out of the competitive race.
Samsung's strategy includes manipulating yield rates. What constitutes a production-worthy yield at a new node is the most ambiguous aspect. Following TSMC's approach, true production is when external customers place orders and successfully receive their products at current yield levels—a concept known as commercial production.
At Samsung, initial customers for each new node are typically internal, with risk production starting at low yield stages while publicly announcing mass production.
Announcing mass production based on single-digit yield rates during development is purely promotional and lacks substantive significance. In cases where yield rates are insufficient, customers typically bear the cost of defective wafers. Given equal densities, customers preferentially place orders with the fab offering the highest yield rates. In situations where both density and yield rates lag, only reduced contract fees can attract sporadic customers, yet this approach fails to generate any profit for the wafer fab.
It's important to note that manufacturers sometimes disclose yield rates as high as 60% or even 80%, but these figures often pertain to simpler chips like ASICs for mining rigs. Conversely, yield rates for complex chips like mobile application processors (APs) may be below 50%, and for large-area chips like GPUs, it could be just over 20%.
Even with the same 7nm process, yield rates can differ significantly depending on the product. Manufacturers tend to highlight their best figures while
withholding less favorable data, a common industry practice.
The timing of mass production and yield rates at wafer fabs is a gray area ripe for manipulation. This comparison goes beyond simple process node equivalence and involves transistor densities per unit area and the actual timing and yield rates required to secure commercial customer orders—this defines true commercial production.
In 2020, Samsung announced the mass production of 5nm chips, seemingly outpacing its rivals. However, comparing transistor densities and yield rates reveals a completely different outcome.
How can we achieve 5nm without EUV？
In the preceding sections, we discussed the concepts of 5nm in the past and present. Simply put, 20 years ago, referring to 5nm meant linewidths and gate lengths of transistors. Today, however, 5nm represents a symbolic node in the fabrication process. The true measure of progress lies in the transistor density per unit area rather than just this symbol.
Next, we will explain through a series of discussions how to achieve so-called "5nm" and "3nm" without EUV lithography. Dr. Lin Benjian's lecture "Optical Microlithography Shrinks ICs a Millionfold" provides detailed insights into this topic. We'll start with a fundamental optical resolution formula (hint: no advanced math required, keep reading to understand):
Half Pitch = k1λ / sinθ.
Half Pitch: As depicted in Figure 2 of the article, it refers to half of the pitch, which is the linewidth/gate length plus the spacing between lines, multiplied by 1/2.
k1: A coefficient related to the process, crucial for reducing Half Pitch, which is the primary focus of all semiconductor fab lithography engineers and the core of our discussion.
λ: The wavelength of the light source used in lithography, which has decreased from 436nm for g-line to 13.5nm for EUV, a goal pursued by lithography equipment manufacturers.
sinθ: Related to the angle at which the lens focuses light onto the imaging plane, primarily determined by the lens itself, also a goal for lithography equipment manufacturers.
However, since the wavelength of light changes in different media, when considering how to increase resolution, the refractive index (n) of the medium between the lens and the wafer must also be taken into account. Thus, the formula becomes Half Pitch = k1λ / (n sinθ) (Note: n sinθ is the numerical aperture (NA) of the lithography tool).
Figure 3: Schematic diagram of light focusing and imaging through a lens system, where n represents the refractive index of the medium, and θ represents the focusing angle of the lens.
Using a 193nm immersion lithography machine as an example, with a k1 value of 0.28, a refractive index (n) of water as 1.44, and sinθ as 0.93, the Half Pitch calculation is (0.28 × 193) / (1.44 × 0.93) = 54.04 / 1.3392 ≈ 40nm, indicating a resolution of 40nm.
Therefore, to enhance the resolution of lithography machines, adjustments can be made to the variables in the formula by expanding the denominator or reducing the numerator, leading to four possibilities: increasing the focusing angle to improve sinθ, raising the refractive index (n) of the medium, lowering the k1 coefficient, or utilizing a light source with a shorter wavelength (λ). Among these options, reducing the k1 coefficient stands out as one of the most significant breakthroughs currently pursued by semiconductor fabs and warrants focused attention.
Increasing sinθ: Developing complex and large lenses
sinθ is determined by the angle at which the lens focuses light, and a higher sinθ corresponds to higher resolution. The lenses used in lithography machines come in various sizes, thicknesses, and curvatures. They are meticulously stacked and assembled after precise calculations, often requiring crane installations. Currently, the lens systems of lithography machines cost nearly $60 million, with EUV lens systems exceeding $100 million.
Figure 4: 0.9NA lithography machine lens system, where NA (Numerical Aperture) = n × sin θ
Making it so complex is also aimed at pushing sinθ as close to the theoretical maximum of 1 as possible.
Currently, ArF lithography machine lenses can achieve a sinθ value of 0.93, while EUV lithography machines can only reach 0.33. The target for Hyper-NA EUV is 0.75, which is also ASML's ultimate goal. If no new technological breakthroughs emerge in the future, this could potentially mark the end of physical lithography technology for semiconductor chips.
Shortening Wavelength: Precise Matching of Materials and Lenses.
Shortening wavelength primarily relies on changing the light source, such as g-line, i-line UV (ultraviolet), KrF, ArF DUV (deep ultraviolet), and currently, EUV (extreme ultraviolet) at a wavelength of 13.5nm. Further shortening of wavelength leads to X-rays.
Changing the light source allows achieving the desired wavelength, but the materials of the lenses must also be correspondingly adjusted, with fewer material options available as wavelengths decrease.
Another solution involves incorporating mirrors into the lens assembly (yellow section in the diagram below). Such lens assemblies are known as reflective-refractive optical systems. Regardless of the light wavelength, incidence and reflection angles on mirror surfaces are equal. By substituting lenses with mirrors, tolerance for light wave bandwidth can be increased.
Figure 5: Lens system used in 193nm ArF lithography machines, incorporating mirrors between the lens assemblies as shown in the diagram.
When it comes to the 13.5nm wavelength of EUV, the entire lens system employs mirrors, known as a full reflective optical system. This system must be designed to allow the light beams to pass without obstructing the mirrors. Additionally, compared to the tolerance of errors in lens transmission angles, mirror reflection angles require much greater precision.
Changing the light source not only affects the lens materials but also involves the materials for photoresists, encompassing chemical properties, transparency, photosensitivity, and other characteristics. This constitutes a significant undertaking, requiring numerous materials and formulations to address different layers in the manufacturing process. Among these, photosensitivity is crucial for cost-effective manufacturing, as even a few seconds more exposure time per chip is considered an unbearable cost.
Increasing the refractive index ( n ): Immersion lithography technology
In the quest to enhance resolution, another approach involves adjusting the medium between the lens and the wafer. The immersion lithography technique, proposed by TSMC's Deputy Director of Research, Lin Benjian, replaces the medium from air, which has a refractive index close to 1, with water, which has a refractive index of 1.44. This effectively reduces the equivalent wavelength from 193nm to approximately 134nm, scaled by the refractive index of the medium.
Figure 6: Differences between dry lithography systems and immersion lithography systems
Immersion lithography technology allows semiconductor processes to continue using the same wavelength and masks by simply introducing water between the lens and the wafer. The theory is straightforward, but the challenge lies in practical implementation. For instance, in immersion systems, air bubbles can form in the DI water (deionized water), which must be completely removed. Moreover, the water must flow rapidly and uniformly to ensure even distribution and maintain imaging quality.
As we have learned, ASML's immersion lithography machine, the Alpha tool, underwent 7-8 modifications specifically with Lin Benjian's team at TSMC's Nanke facility over a period of more than two years. Even after completing the Alpha machine, the Beta version required extensive manpower at the wafer fab to process countless wafers, reducing initial defects from thousands to hundreds or tens, and ultimately to zero. This process was arduous and demanding.
Reducing k1: Resolution Enhancement Techniques (RET).
The final approach to improving resolution is to reduce the k1 value, which is crucial for lithography process engineers in semiconductor fabs, especially for creating 5nm chips using DUV (Deep Ultraviolet) lithography.
The first challenge to address is "vibration prevention", akin to image stabilization in photography, where efforts are made to minimize relative vibrations between the wafer and the mask during exposure. This ensures more precise exposure patterns and restores resolution lost due to vibrations. The second challenge is "minimizing unwanted reflections," aiming to eliminate unnecessary reflections from the wafer surface during exposure. Improvements in these parameters have shown that k1 can be controlled to around 0.65.
To further enhance resolution, dual-beam imaging techniques are employed, including off-axis illumination and phase-shifting masks. Off-axis illumination adjusts the angle of light incidence, allowing oblique light to enter the mask. By adjusting these angles, the interference between these two beams enhances resolution and increases depth of field. Phase-shifting masks modify the mask to introduce a 180-degree phase difference between light passing through adjacent transparent regions. Both approaches can halve the k1 value individually, but they fall under the concept of dual-beam imaging and cannot be used together. These methods can typically reduce k1 to around 0.28.
Further reduction of k1 involves the use of multiple masks, known as multiple patterning, a technique where intricate patterns are split between two or more masks with looser patterns, alternating exposures on the wafer (as shown in Figure 7).
Figure 7: Schematic diagram of masks used in a 28nm lithography machine. Light passes through white apertures, projecting yellow dots onto the photoresist on the wafer. By using two masks for separate exposures, resolution enhancement is achieved.
However, doubling the exposure times results in a halving of the wafer per hour (WPH) output rate, assuming it remains unchanged. Multiple exposures also decrease yield rates. When combined with reduced output, this creates an intolerable burden for the semiconductor industry, which values cost efficiency above all else. The increased exposure times inevitably lead to lower yields, making yield rates the only way engineers can save themselves.
On immersion lithography machines, the use of techniques such as optical proximity correction (OPC) and joint optimization of light sources and masks can push k1 values down to 0.2, achieving a resolution of 28nm. With double exposure, k1 can be reduced from an initial 0.28 to 0.14, achieving a resolution of 20nm. Quadruple exposure can further decrease k1 to 0.07, achieving a resolution of around 10nm, even surpassing the 11.5nm resolution of EUV lithography machines. This forms the theoretical basis for immersion lithography's multiple exposure approach in achieving 7nm, 5nm, and even 3nm nodes.
Table 4: Theoretical Achievable Resolutions Using Various Resolution Enhancement Techniques for 193nm Immersion Lithography Machines
While the theory sounds simple, its practical application is far from easy, especially with the critical technology of self-aligned multiple patterning (SAMP), which allows for significant reduction in k1 values. The key to this technology lies in the overlay accuracy of lithography machines, determining alignment precision between layers on chips and thereby affecting the yield of multiple exposures.
One approach to improving overlay accuracy is acquiring higher precision equipment, such as the 2100i DUV lithography machine. Additionally, each semiconductor fab has its own unique set of techniques. Currently,*is the only company worldwide that can achieve nearly single machine overlay (DCO) using multiple machine overlay (MMO), aside from lithography machine performance. There are two pieces of data for reference:*uses an MMO:2.5nm 1980ci lithography machine with quadruple exposure yield exceeding 80%, while the mainland factory with an MMO:1.5nm 2050i and quadruple exposure has achieved a yield close to 50% after two years of continuous efforts.
Last year, the Interuniversity Microelectronics Centre (IMEC) in Belgium released a technical scheme for achieving 5nm using immersion lithography machines with octuple exposure.
In other technological routes, IMEC and Mentor jointly developed the Self-Aligned Lithography and Etching (SALELE) technology, which does not require additional redundant metal and capacitors. They also explored a lithography method that bypasses traditional mask usage by focusing on material research, synthesizing polymers first and then inducing specific chemical interactions through heating to achieve "Directed Self-Assembly" (DSA), forming structures a quarter of the original size.
Furthermore, due to EUV being easily absorbed and unable to increase refractive index (n value) like DUV with water immersion, ASML is improving through High-NA and Hyper-NA to enhance sinθ, but this path will ultimately reach its limits. Therefore, in the semiconductor manufacturing process, significantly reducing k1 through multiple exposures remains a crucial technology, regardless of whether it's DUV or EUV. This also highlights the increasing importance of deposition and etching equipment. AMAT, LAM, and TEL are vigorously developing related technologies, including more complex pulses, finer control, and higher power tools, especially atomic layer deposition and etching technology, which will alter traditional process routes.
Returning to the transistor density table in the second part of the article, whether future nodes are labeled "3nm" or "N+4" is not the focus; what matters is whether chip transistor density can be significantly increased.
