Explanation of Common Semiconductor Defect Terminology

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2024-03-14 10:50:37 686

Crystal Growth Defects

1. Dislocation: Dislocations, also known as disclinations, are internal microstructural defects in crystal materials where atoms are locally arranged irregularly. From a geometric perspective, dislocations are a type of linear defect within crystals that serve as boundaries between slipped and unslipped regions, significantly impacting the material's physical properties, especially its mechanical characteristics.

Cause: Dislocations can arise during crystal growth when dislocations from seed crystals or insoluble solid particles near the solid-liquid interface fall into the crystal. Temperature gradients or fluctuations near the interface, mechanical vibrations, and rapid cooling after crystal growth can all contribute to the formation of dislocations. Dislocations are triangular for (111) planes, square for (100) planes, and rhombic for (110) planes.

2. Impurity Striations: Impurity striations, also known as resistivity striations, appear as alternating light and dark layering patterns on the longitudinal section of crystals after chemical etching. These striations exhibit a specific distribution pattern, forming ring-like distributions on cross-sections perpendicular to the growth axis and layered distributions along the longitudinal sections parallel to the growth axis. They reflect the shape of the solid-liquid interface front during crystallization.

Cause: Impurity striations form due to minor periodic temperature fluctuations near the solid-liquid interface caused by gravity-induced natural convection, stirring-induced forced convection, and variations in crystal growth rates due to local temperature changes. These factors lead to fluctuations in the effective impurity segregation coefficient, resulting in corresponding changes in impurity concentration distribution within the crystal and the formation of impurity striations.

Solution: Adjusting the thermal field to ensure axial symmetry and aligning the crystal's rotation axis as much as possible with the central axis of the thermal field while suppressing or reducing melt convection can promote uniform impurity distribution within the crystal. The use of magnetic field pulling processes or crystal pulling under zero-gravity conditions can help eliminate impurity striations.

3. Pits: Pits are local areas on a crystal's cross-section that exhibit faster etching rates, resulting in depressions on the surface after chemical etching. Higher etching temperatures and longer etching times lead to deeper pits that may even penetrate through the crystal.

4. Voids: Voids are irregularly shaped, varying-sized cavities on the cut surface of a single crystal. Cause: During the growth of a single crystal in a gaseous atmosphere, gases with high solubility in the melt at lower temperatures become supersaturated as the crystal grows. If the crystal grows too rapidly, gases cannot escape the melt promptly, leading to the formation of voids within the crystal.

5. COP Defects: COP defects are small void-like native microdefects detected under a laser particle counter after etching with a No.1 cleaning solution. Preventing and eliminating COP defects requires comprehensive measures from crystal growth, impurity control, processing techniques, and quality control to enhance the quality and performance of monocrystalline silicon. Additionally, appropriate annealing treatments can reduce or eliminate native defects.

6. Oxygen-Induced Stacking Faults (OISF): OISF occurs at the silicon dioxide-silicon interface during thermal oxidation, where self-intestinal silicon atoms diffuse to stress or defect sites (nucleation centers) and form and grow OISFs. The radial distribution of point defects in crystals during growth, determined by growth parameters such as growth rate and temperature gradient at the solid-liquid interface, is associated with the formation of OISFs through interactions between vacancies and self-interstitials, leading to anomalous oxygen precipitation.

7. Twinning: Twinning results in two distinct regions with different metal lusters on a crystal's fracture surface, typically separated by a straight line. Cause: Twinned crystals form due to the presence of solid particles at the solid-liquid interface, mechanical vibrations, excessively fast crystal pulling speeds, sudden temperature changes, and local undercooling in the melt, all of which can create nucleation centers and lead to twinning.

8. Inclusions: Small crystals exist within a germanium single crystal that have orientations different from the matrix.

9. Polycrystalline: Multiple single crystals with different orientations within a crystal. On the cross-section of a single crystal, after grinding or chemical etching, various regions exhibit different metallic lusters.

Mechanical Processing Defects

1. Mechanical Stress Defects: During mechanical processing, cutting surfaces can introduce mechanical stress defects. Even after grinding, these defects may not be visible, but they can reappear after chemical etching and may lead to dislocations.

2. Cutting Blade Marks: Traces left by cutting tools during the cutting process.

3. Cause: Uneven cutting tools, significant oscillation during processing, uneven distribution of diamond particles, and excessive cutting speeds.

4. Root Fractures: Circular fractures along the edge of a wafer following blade marks.

Cause: Improper blade installation and excessively high cutting speeds causing the wafer to fracture before being fully cut.

5. Tilted Wafers: Areas where both surfaces of a wafer are not parallel, causing some regions to remain unground after grinding, known as tilted wafers.

Cause: Loose blade installation, high cutting speeds leading to excessive resistance beyond the blade's tension, resulting in lateral movement and producing tilted wafers.

6. Concave and Convex Wafers:

Cause: Loose blade installation, excessive cutting speeds, and thermal deformation of the wafer during polishing due to temperature effects.

7. Scratches: Clear marks of scratches appearing during grinding or polishing processes.

Cause: Presence of large, hard particles in abrasives or polishing compounds, excessively hard local areas on mechanical polishing pads.

8. Cracks: Microscopic gaps within wafers or crystals.

Cause: Thermal or mechanical stresses.

9. Edge Chipping: Localized partial damage along the edge of a wafer.

Cause: Impact forces during slicing, etching, cleaning, sorting, or packaging processes causing edge chipping.

10. Notches and Corners: Localized damages penetrating through both sides of a wafer.

Cause: Impact forces during slicing, etching, cleaning, sorting, or packaging processes causing edge chipping.

11. Irregular Shapes: Occurrence of wafers or blocks with shapes approximating ellipses, rhombuses, or cones.

Cause: Improper tool application.

12. Burr: Multiple fractures along the edge of a wafer, resulting in an unclear outline.

Cause: Improper operation during cutting or grinding.

13. Surface Contamination: Fingerprints, water stains, organic substances, dust, and corrosion oxidation on the surface.

Cause: Improper cleaning of wafers leading to water stains, direct contact of fingers with the wafer surface, prolonged exposure to humid environments causing surface oxidation, presence of organic substances or dust on the wafer surface, oxidation during the wafer etching process.

14. Stickiness: Surfaces sticking together due to moisture.

15. Total Thickness Variation (TTV): The difference between the maximum and minimum thickness measurements in silicon wafers, referred to as the total thickness variation. This value is a crucial standard for evaluating the quality of silicon wafers.

16. Flatness: The difference between the highest and lowest points between the wafer surface and a reference plane, a surface property. When processed into an almost flat plane, there are no Newton rings or almost linear interference fringes; when processed into a spherical surface, circular interference patterns appear, with fewer rings indicating a flatter surface. In cases where the processed surface is neither flat nor spherical, irregular interference fringes occur.

Cause: Improper operation, equipment malfunctions, unsuitable temperature or humidity conditions.

17. Bow: A measure of the concave or convex deformation in the center surface of a wafer, unrelated to any thickness changes, representing a bulk property of the wafer rather than a surface characteristic.

18. Warp: The difference between the maximum and minimum distances between the center surface of a wafer and a reference plane, illustrating the maximum warping of the wafer and representing a bulk property rather than a surface feature.

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Explanation of Common Semiconductor Defect Terminology

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