Integrated scale and dimension

slkor|Technical Blogs|Technical Blogs|

2022-04-02 00:13:25 126

01 Scale of integration

Scale, generally understood asSize, The measured length,The prescribed limits,It can be extended to norms and statutes.In this paper, scale refers to the size or size of the described object.according toAnalyze the scale of integration from small to large, let's start with the smallest elementary particle!

1、fundamental particle

The known world of mankind consists of 61 kinds of Elementary Particles.

61 kinds of elementary particles are divided into quark, lepton and boson. (boson) Three categories.

Among them, only Electron, photon and neutrino are stable particles that exist in nature and can act on the macroscopic world. The famous quark, confined in compound particles such as protons and neutrons, cannot be released for life.

electron (lepton): The electron is the basic particle which is most fully known and widely used by human beings. Today, modern science and technology basically revolve around electronics. Without electronics, the whole world would stagnate.(lepton): The electron is the basic particle which is most fully known and widely used by human beings. Today, modern science and technology basically revolve around electronics. Without electronics, the whole world would stagnate.

photon (Boson): Photon was applied earlier than electron, and it has been applied since ancient times. Nowadays, photons are indispensable from daily life to the latest scientific field.

neutrino (lepton): Neutrinos are difficult to detect, so they are called mysterious particles. Although they are not widely used at present, they are regarded as a kind of particle with great potential. It is extremely fast, close to the speed of light, and can pass through all objects unimpeded. It can be used in neutrino communication, stratum scanning and other fields in the future.

And those basic particles that can't exist independently in nature can't deal directly with the macro world, so they can't be practical, and their impact on human beings is far less than that of electrons, photons and neutrinos.

2、atom

We scale up to atoms.。

Among the 118 known elements, there are 92 elements from nature, and the rest elements are synthesized artificially. The smallest unit representing an element is called an atom, and different atoms make up different substances.

The structure of an atom is composed of a nucleus and electrons moving around the nucleus. The nucleus only accounts for one hundred billionth of the atomic volume. Therefore, the atomic volume is determined by the extra-nuclear electrons.

There is wave-particle duality of electrons. It doesn't have a definite orbit like the motion of macroscopic objects. It's impossible to predict where it will appear in the extra-nuclear space at a certain moment. We only know the probability that it will appear somewhere. Like a negatively charged cloud around the nucleus, it is called "electron cloud".

Take silicon, the most commonly used element in our semiconductors, as an example. There are 14 electrons outside the nucleus of silicon, including 2 electrons in the first layer, 8 electrons in the second layer, and 4 valence electrons in the outermost layer.

There are no obvious free electrons in the crystal. The four outermost electrons of the silicon atom are not as active as the conductor, nor are they tightly bound as the insulator. Their activity is between the conductor and the insulator, and they have semiconductor properties. Silicon can conduct electricity, but its conductivity is not as good as that of metal, and it increases with the increase of temperature.

The atomic scale, the outermost layer of an atom does not have a precise definition. The radius of an atom is usually measured according to the average nuclear distance between adjacent atoms. So, what is the distance between silicon atoms in a silicon crystal?

The most basic geometric unit of a crystal is called a Unit Cell. A silicon crystal is a face cube with a side length of 0.543nm. Take one face of the silicon atom cell as a plane, and the silicon atoms are arranged as shown in the following figure. The minimum spacing of silicon atoms in this plane is 0.384nm, and the arrangement width of three silicon atoms is 1.152nm.

So, how many silicon atoms are there in a cubic nanometer?

In the unit cell of a face-centered cube composed of silicon atoms, there are one silicon atom in each of the eight vertices and six faces, and there are also four silicon atoms, which are located at 1/4 of the four spatial diagonals, and the average number of atoms in each silicon unit cell is 8 (8 × 1/8+6 × 1/2+4 = 8).

The unit cell side length of silicon is a (lattice constant), and a = a=5.4305?(0.543nm) at 300K K.。

8 ÷（0.5433）=49.97≈50，That is to say, the number of silicon atoms in 1 nm is 50, and the same result can be obtained by calculating the density of silicon material and the mass of silicon atoms.

In order to improve the conductivity of silicon, a small amount of pentavalent elements are doped to form N-type semiconductor, or a small amount of trivalent elements are doped to form P-type semiconductor.

No matter what kind of elements are doped, the lattice structure of silicon will not change basically, so the distance between atoms will not change, 1 nm & nbsp; The number of atoms will not change, it is still 50.

At the nanometer scale, atoms can be counted.

3、From atoms to functional cells

What is a Function Cell? We define it as the smallest unit of function. In integrated circuits, transistors can be defined as functional cells. Of course, resistors, capacitors, inductors and diodes are also functional cells.

The function of a cell is made up of atoms, and the realization of its function is achieved by controlling electrons. In other words, the function of a functional cell is given by electrons, and if it can reasonably control electrons, it will have corresponding functions.

The realization of its functions comes from the actual needs, human wisdom and those great inventions or discoveries.

Let's take the most typical functional cell transistor in integrated circuits as an example.

The reason why a transistor can become a functional cell is that it can effectively control electrons.

The following figure shows the current mainstream FinFET transistor. By applying a reasonable voltage to the Gate, electrons can flow from the Source to the Drain, thus generating current and conducting.

Through the turn-on and turn-off of transistors, different states can be represented, and when multiple transistors are combined together, different logic circuits can be formed, thus accomplishing different functions.

As long as it can perform the same function, the smaller the volume of functional cells, the better. How small can functional cells be?

For the existing silicon-based transistor, it is roughly restricted by two factors, one is the smallest structure width in the transistor, and the other is the area (volume) occupied by the transistor itself.

From the above analysis, we know that the width of three silicon atoms arranged side by side is more than 1nm. Can the minimum structure width of the transistor reach or even be less than 1nm? It's hard to judge now. Besides the difficulty in manufacturing such a small width, the transistor that works according to the existing theory is also difficult to work normally.

A new type of transistor, such as a single atom transistor, has a minimum structure width of only one atom. The transistor can be turned on and off by operating a single atom.

It is said that the energy consumption of monoatomic transistors will be only one ten thousandth (1/10000) of that of silicon-based transistors, which is a decisive advantage for future applications.

4、From functional cells to normal systems

Functional cells can be very small, and the current technology can support the integration of more than 10 billion transistors on a chip the size of a fingernail. A plurality of functional cells can form a Function Block, which in turn forms a Function Unit, and a plurality of function units form a MicroSystem.

However, for human beings, the scale of their products needs to be suitable for human needs, and must be equal to the scale of human beings themselves.

For example, mobile phones and computers, the former needs to be held in the hands frequently, so it needs to be the size of a human hand, while the latter needs to be placed on the desktop or knees, so it is the size of the human body horizontally.

This kind of system, which we call a Common System, means a system that ordinary people can contact and often use. Systems are often composed of microsystems, functional units, and finally functional cells.

Because of the need to match the scale of human beings, the scale of the system will not change much even if the development of science and technology is advanced. However, in order to meet more functional requirements of human beings, the functional cells contained in the system will continue to increase, that is, the Function Density of the system will continue to increase.

Moreover, in the process of the development of human civilization, this trend will continue, which is also in line with the description of the law of function density.

5、From constant system to large system

In addition, there is another kind of system, which serves people, but not individuals, but groups, so its scale can be very large. We call this kind of system Giant System. For example, manned spaceflight system, wireless communication network system, GPS global satellite positioning system and so on.

Large-scale systems are usually very complex, and generally consist of many constant systems, microsystems or functional units.

For example, the GPS system is divided into three parts: the space part, which consists of 24 satellites; The ground part consists of main control station, monitoring station and ground antenna; The user part, that is, various GPS signal receivers.

The GPS system can perform real-time high-precision positioning, speed measurement and accurate timing for various mobile users such as ground vehicles, ships, airplanes, satellites and spaceships.

Like ordinary systems, large systems will increase their functional density in order to meet more functional requirements, and this trend will continue with the development of human civilization, which is also in line with the description of the law of functional density.

6、Scale summary of integration

Here, we summarize the scale of integration with two figures.We divide the electronic system into six levels according to the hierarchy, which is called the six-level classification of electronic system.。Among them, functional cell is the smallest functional unit, functional cell → functional block.→Functional units, which are three different functional units, form a microsystem.→Constant system→System, as shown in the figure below.

Then, we analyze the functional cells and divide them into four levels according to the hierarchy: basic particles make up atoms, atoms make up unit cells, and unit cells make up functional cells.

In this paper, from elementary particles to the most complex system that human beings can realize at present, we divide them into 10(4+6) levels according to the scale. Among them, functional cells are the most critical link, the basic unit and carrier of functions, just like human cells, the constituent unit of human life and the carrier of wisdom.

Every level or link requires different people to explore, realize, innovate and develop, and integrate human wisdom into it.

02 集成的维度

The world that human beings can perceive has only three spatial dimensions, plus time, which is often called four-dimensional space-time.

The 11-dimensional space-time described in string theory can't prove its real existence. Even the existence, like the elementary particles confined in the microscopic world, can't be perceived in the macroscopic world of human beings, so it has almost no influence on human activities.

In our usual understanding, zero dimension is a point, one dimension is a line, two dimensions are a plane, and three dimensions are a solid.

Integration is the process of bringing different units together and realizing their specific functions. Therefore, zero-dimensional points and one-dimensional lines are not suitable for integration. In reality, the main integration methods are two-dimensional planar integration and three-dimensional stereoscopic integration.

In practice, it's a bit reluctant to classify integration only by two-dimensional and three-dimensional. For example, some people use "false 3D" and "true 3D" to distinguish different types of chip stacking modes.

In this paper, we divide integration into five dimensions: 2D, 2D+, 2.5D, 3D and 4D, in order to facilitate the classification and differentiation of integration, and at the same time, to be compatible with the current mainstream views.

In addition, we give two important criteria, physical structure and electrical interconnection.

The integration described below is mainly aimed at the field of integrated circuit packaging, and can be analogized to other fields.

1、2Dintegrated

2DIntegration means that all chips and passive devices are horizontally mounted on the surface of the substrate.

Create a coordinate system with the bottom left corner of the upper surface of the Substrate as the origin, the plane on which the upper surface of the substrate is located as the XY plane, and the normal of the substrate as the Z axis.

Physical structure: All chips and passive devices are installed on the substrate plane, which is in direct contact with the XY plane, and the wiring and vias on the substrate are located below the XY plane; Electrical interconnection: all need to pass through the substrate (except a few bonding points directly connected by bonding wires).

Our most common 2D integration technology is applied to MCM, some SiP and PCB.

MCM（Multi Chip Module）Multi-chip module is a complete component in which multiple bare chips are mounted on the same substrate in high density.

In the traditional packaging field, all packages are chip-oriented, serve the chip, protect the chip, scale up and connect electrically, without any concept of integration. With the rise of MCM, the concept of integration comes into being in packaging, so the essence of packaging has also changed. MCM shifts the concept of packaging from chips to modules, components or systems.

The process route of 2D integrated SiP is very similar to MCM. The main difference between 2D integrated SiP and MCM is that the scale of 2D integrated SIP is larger than MCM's, and it can form an independent system.

2D integration diagram

In addition, FOWLP-based integration, such as INFO, although there is no substrate, can also be attributed to 2D integration. At present, the transistor arrangement in integrated circuits also basically belongs to 2D integration.

2D integration is the simplest for EDA design tools. The following figure shows the 2D integration design implemented in EDA tools.

2D integrated design realized in EDA tools

2、2D+integrated

2D+ integration refers to the traditional chip stack integration connected by bonding wires. Some people may ask, isn't chip stacking 3D? Why should it be defined as 2D+ integration?

Mainly based on the following two reasons: 1)3D integration refers to integration through 3D TSV to a large extent at present. In order to avoid conceptual confusion, we define this traditional chip stack as 2D+ integration; 2) Although the physical structure is 3D, its electrical interconnection needs to pass through the substrate, that is, it is bonded to the substrate by bonding wires first, and then the electrical interconnection is carried out on the substrate. This is the same as 2D integration. Compared with 2D integration, it is improved by the structural stacking, which can save the packaging space, so it is called 2D+ integration.

Physical structure: All chips and passive devices are located above the XY plane, some chips do not directly contact the substrate, and the wiring and vias on the substrate are located below the XY plane; Electrical interconnection: all need to pass through the substrate (except a few bonding points directly connected by bonding wires).

Several integrations shown below are 2D+ integrations.

Schematic diagram of 2D+ integration

In addition, the integration mode of PoP (Package on Package) class can also be judged according to its physical structure and electrical connection, which can be attributed to 2D+ integration.

EDA design tools have always supported 2D+ integration. The following figure shows the 2D+ integration design implemented in EDA tools.

2D+ Integrated Design Implemented in EDA Tools

3、2.5D integration

2.5D, as its name implies, is between 2D and 3D. It usually refers to a dimension with the characteristics of 2D and some 3D. In reality, there is no such dimension as 2.5D.

Physical structure: All chips and passive devices are above XY plane, and at least some chips and passive devices are installed on Interposer. There are wiring and vias of interposer above XY plane, and wiring and vias of substrate below XY plane. Electrical interconnection: the Interposer can provide the electrical connection of the chips located on the interposer.

The key of 2.5D integration lies in the Interposer, and there are generally several situations: 1) whether the interposer is made of silicon, 2) whether the interposer is made of TSV, and 3) whether the interposer is made of other materials; On the silicon interposer, we call the via through the interposer TSV, and on the glass interposer, we call it TGV.

The integration with TSV in the silicon interlayer is the most common 2.5D integration technology. The chip is usually connected with the interlayer through MicroBump, and the silicon substrate as the interlayer is connected with the substrate by Bump. The surface of the silicon substrate is wired through RDL, and TSV serves as the channel for the electrical connection between the upper and lower surfaces of the silicon substrate. This 2.5D integration is suitable for the situation of large chip scale and high pin density, and the chip is generally installed on the silicon substrate in the form of FlipChip.

Schematic diagram of 2.5D integration with TSV

The 2.5D integrated structure of silicon Interposer without TSV is generally shown in the following figure. A large bare chip is directly mounted on the substrate, and the connection between this chip and the substrate can be made by Bond Wire or Flip Chip. Because of the large area, several smaller bare chips can be mounted above the large chip, but the small chip cannot be directly connected to the substrate, so an interposer needs to be inserted. A plurality of bare chips are installed above the intermediate layer, and RDL wiring is arranged on the intermediate layer, so that the signals of the chips can be led out to the edge of the intermediate layer, and then connected to the substrate through Bond Wire. This kind of Interposer usually does not need TSV, but only needs to be electrically interconnected by wiring on the upper surface of Interposer, which is connected to the package substrate by Bond Wire.

Schematic diagram of 2.5D integration without TSV

Now, EDA design tools have good support for 2.5D integration. The following figure shows the 2.5D integration design realized in EDA tools.

2.5D integrated design realized in EDA tools

4、3D integration

The main difference between 3D integration and 2.5D integration is that 2.5D integration is wiring and punching on Interposer, while 3D integration is punching (TSV) and wiring (RDL) directly on the chip to electrically connect the upper and lower chips.

Physical structure: All chips and passive devices are located above the XY plane, and the chips are stacked together. There are TSV passing through the chips above the XY plane, and wiring and vias of the substrate below the XY plane. Electrical interconnection: the chips are directly electrically connected through TSV and RDL.

3D integration is mostly used in similar chip stacks. Many identical chips are vertically stacked together and interconnected by TSV passing through the chip stacks, as shown in the following figure. Similar chip integration is mostly used in memory integration, such as DRAM Stack, FLASH Stack and so on.

Schematic diagram of 3D integration of similar chips

In 3D integration of different chips, two different chips are generally stacked vertically, electrically connected together by TSV, and interconnected with the underlying substrate. Sometimes, RDL needs to be made on the chip surface to connect the TSV of the upper and lower layers.

Schematic diagram of 3D integration of different chips

In addition, the current 3D Nand Flash is a 3D integration technology, which directly makes multi-layer memory cells on the chip.In addition, the current 3D Nand Flash is a 3D integration technology, which directly makes multi-layer memory cells on the chip.

Now, EDA design tools have good support for 3D integration. The following figure shows the 3D integration design implemented in EDA tools.

3D integrated design realized in EDA tools

5、4D integration

We introduced 2D, 2D+, 2.5D, 3D integration and 4D integration. How are they defined?

In several integrations mentioned above, all chips, interposer and substrates have their Z axes vertically upward in the three-dimensional coordinate system, that is, all substrates and chips are installed in parallel. In 4D integration, this situation has changed.

When the XY planes of different substrates are not parallel, that is, the Z axis directions of different substrates are offset, we can define this kind of integration as 4D integration. Physical structure: A number of substrates are installed in a non-parallel way, and each substrate is equipped with components, so the installation methods of components are diversified. Electrical interconnection: the substrates are connected by flexible circuits or soldering, and the electrical connections of chips on the substrates are diversified.

Schematic diagram of 4D integration based on rigid-flexible substrate

Schematic diagram of gas-tight ceramic 4D integration

The definition of 4D integration is mainly about the orientation and interconnection of multiple substrates, so in 4D integration, each substrate may include 2D, 2D+, 2.5D and 3D integration methods.

The 4D integration technology can solve the problems that can't be solved by parallel three-dimensional stacking, provide more and more flexible chip installation space, solve the heat dissipation problem of high-power chips, and pay attention to the airtightness problem in aerospace and other fields.

Now, EDA design tools also have good support for 4D integration. The following figure shows the 4D integration design implemented in EDA tools.

4D integrated design realized in EDA tools

4D integration technology improves the flexibility and diversification of integration. Looking forward to the future, 4D integration will certainly occupy a place among various integration dimensions, and will become an important integration technology after 2D, 2D+, 2.5D and 3D integration technologies.

In the strict physical sense, according to the existing human cognition, all objects are three-dimensional, and the two-dimensional foil does not exist, so the four-dimensional space needs to be verified.

In order to distinguish different integration modes, we divide them into five integration dimensions: 2D, 2D+, 2.5D, 3D, 4D.

6、Dimension summary of integration

Here, we use a figure to summarize the dimensions of integration, as shown in the following figure, EDA design drawings containing five integration dimensions and the specific integration types contained in each dimension.

03 总结

Generally, integration refers to human activities, not natural processes. Therefore, integration is also an important means for human beings to transform the world.

In this article, we analyze modern electronic integration technology from two aspects: scale and dimension. Both belong to the category of space, one represents the size of space and the other represents the orientation of space.

The scale of integration ranges from the smallest elementary particle to the most complex large system, and is described in 10 levels. The integrated dimension defines five dimensions for classification and description.The scale of integration ranges from the smallest elementary particle to the most complex large system, and is described in 10 levels. The integrated dimension defines five dimensions for classification and description.

Our description of integration from the spatial axis is sufficient.

Prev:: I am a sand, so I became a chip like this

Next:: Analysis | Shallow Mainland Electric Drive System EMR4

Integrated scale and dimension

Advisory Service